The advanced Application-Specific Integrated Circuit (ASIC) manufacturer, GUC, announced that its HBM3 IP solution, based on the Taiwan Semiconductor Manufacturing Company (TSMC) 5nm process technology, has passed the 8.4 Gbps tape-out verification. The platform incorporates a comprehensive HBM3 controller and Physical Layer IP (PHY IP), as well as vendor HBM3 memory leveraging TSMC's cutting-edge CoWoS® technology.
Currently, HBM memory suppliers have set forth an ambitious roadmap, increasing the transfer rate and memory size from HBM3 to HBM3E/P and further doubling the signal bus width in HBM4. However, the fundamental DRAM timing parameters remain consistent, and the HBM controller is becoming increasingly intricate to enhance bus efficiency.
GUC's HBM3 controller achieves over 90% bus utilization during random access, while maintaining minimal latency. The HBM3 IP from GUC, based on TSMC's 5nm technology, has passed tape-out verification. Earlier this year, they introduced the HBM3 IP utilizing TSMC's 3nm technology. This IP supports TSMC's CoWoS-S and CoWoS-R and can reach the speeds of the next-generation HBM3E/P memory (still under planning). Since 2020, GUC's HBM controller and PHY IP have been implemented in customer-produced HPC ASICs.
